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EBOOK
Author Bhatnagar, Himanshu.
Title Advanced ASIC chip synthesis : using Synopsys Design Compiler, Physical Compiler, and PrimeTime / Himanshu Bhatnagar.
Imprint Boston : Kluwer Academic Publishers, 2002.
Edition 2nd ed.

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Author Bhatnagar, Himanshu.
Subject Application-specific integrated circuits -- Computer-aided design.
Logic design -- Data processing.
Compilers (Computer programs)
Description 1 online resource (xxiv, 328 pages) : illustrations
Edition 2nd ed.
Bibliography Note Includes bibliographical references and index.
Summary Advanced ASIC Chip Synthesis: Using Synopsys Design Compiler Physical Compiler and PrimeTime, Second Edition describes the advanced concepts and techniques used towards ASIC chip synthesis, physical synthesis, formal verification and static timing analysis, using the Synopsys suite of tools. In addition, the entire ASIC design flow methodology targeted for VDSM (Very-Deep-Sub-Micron) technologies is covered in detail. The emphasis of this book is on real-time application of Synopsys tools, used to combat various problems seen at VDSM geometries. Readers will be exposed to an effective design methodology for handling complex, sub-micron ASIC designs. Significance is placed on HDL coding styles, synthesis and optimization, dynamic simulation, formal verification, DFT scan insertion, links to layout, physical synthesis, and static timing analysis. At each step, problems related to each phase of the design flow are identified, with solutions and work-around described in detail. In addition, crucial issues related to layout, which includes clock tree synthesis and back-end integration (links to layout) are also discussed at length. Furthermore, the book contains in-depth discussions on the basis of Synopsys technology libraries and HDL coding styles, targeted towards optimal synthesis solution. Target audiences for this book are practicing ASIC design engineers and masters level students undertaking advanced VLSI courses on ASIC chip design and DFT techniques.
Note Print version record.
Contents Cover -- Table of Contents -- Foreword -- Preface -- Acknowledgements -- About The Author -- CHAPTER 1: ASIC DESIGN METHODOLOGY -- 1.1 Traditional Design Flow -- 1.2 Physical Compiler Flow -- 1.3 Chapter Summary -- CHAPTER 2: TUTORIAL -- 2.1 Example Design -- 2.2 Initial Setup -- 2.3 Traditional Flow -- 2.4 Physical Compiler Flow -- 2.5 Chapter Summary -- CHAPTER 3: BASIC CONCEPTS -- 3.1 Synopsys Products -- 3.2 Synthesis Environment -- 3.3 Objects, Variables and Attributes -- 3.4 Finding Design Objects -- 3.5 Synopsys Formats -- 3.6 Data Organization -- 3.7 Design Entry -- 3.8 Compiler Directives -- 3.9 Chapter Summary -- CHAPTER 4: SYNOPSYS TECHNOLOGY LIBRARY -- 4.1 Technology Libraries -- 4.2 Logic Library Basics -- 4.3 Delay Calculation -- 4.4 What is a Good Library? -- 4.5 Chapter Summary -- CHAPTER 5: PARTITIONING AND CODING STYLES -- 5.1 Partitioning for Synthesis -- 5.2 What is RTL? -- 5.3 General Guidelines -- 5.4 Logic Inference -- 5.5 Order Dependency -- 5.6 Chapter Summary -- CHAPTER 6: CONSTRAINING DESIGNS -- 6.1 Environment and Constraints -- 6.2 Advanced Constraints -- 6.3 Clocking Issues -- 6.4 Putting it Together -- 6.5 Chapter Summary -- CHAPTER 7: OPTIMIZING DESIGNS -- 7.1 Design Space Exploration -- 7.2 Total Negative Slack -- 7.3 Compilation Strategies -- 7.4 Resolving Multiple Instances -- 7.5 Optimization Techniques -- 7.6 Chapter Summary -- CHAPTER 8: DESIGN FOR TEST -- 8.1 Types of DFT -- 8.2 Scan Insertion -- 8.3 DFT Guidelines -- 8.4 Chapter Summary -- CHAPTER 9: LINKS TO LAYOUT & POST LAYOUT OPT. -- 9.1 Generating Netlist for Layout -- 9.2 Layout -- 9.3 Post-Layout Optimization -- 9.4 Chapter Summary -- CHAPTER 10: PHYSICAL SYNTHESIS -- 10.1 Initial Setup -- 10.2 Modes of Operation -- 10.3 Other PhyC Commands -- 10.4 Physical Compiler Issues. -- 10.5 Back-End Flow -- 10.6 Chapter Summary -- CHAPTER 11: SDF GENERATION -- 11.1 SDF File -- 11.2 SDF File Generation -- 11.3 Chapter Summary -- CHAPTER 12: PRIMETIME BASICS -- 12.1 Introduction -- 12.2 Tcl Basics -- 12.3 PrimeTime Commands -- 12.4 Chapter Summary -- CHAPTER 13: STATIC TIMING ANALYSIS -- 13.1 Why Static Timing Analysis? -- 13.2 Timing Exceptions -- 13.3 Disabling Timing Arcs -- 13.4 Environment and Constraints -- 13.5 Pre-Layout -- 13.6 Post-Layout -- 13.7 Analyzing Reports -- 13.8 Advanced Analysis -- 13.9 Chapter Summary -- APPENDIX A -- APPENDIX B.
ISBN 0306475073 (electronic bk.)
9780306475078 (electronic bk.)
6610199949
9786610199945
9780792376446
0792376447
OCLC # 51874139
Additional Format Print version: Bhatnagar, Himanshu. Advanced ASIC chip synthesis. 2nd ed. Boston : Kluwer Academic Publishers, 2002 0792376447 (DLC) 2001050707 (OCoLC)48536509


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