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Title Digital system clocking : high performance and low-power aspects / Vojin G. Oklobdzjja, Vladlmlr M. Stojanovic, Dejan M. Markovic, Nikola M. Nedovic.
Imprint New York : IEEE ; Hoboken, N.J. : Wiley-Interscience, 2003.

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LOCATION CALL # STATUS MESSAGE
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Subject Timing circuits -- Design and construction.
Memory management (Computer science)
Low voltage integrated circuits -- Design and construction.
High performance computing.
Electronic digital computers -- Power supply.
Electric power -- Conservation.
Electrical and Electronics Engineering.
Alt Name Oklobdzija, Vojin G.,
Stojanovic, Vladlmlr M.,
Marković, Dejan M.,
Nedovic, Nikola M.,
Description 1 online resource (xv, 245 pages) : illustrations
Bibliography Note Includes bibliographical references (pages 233-240) and index.
Contents Chapter 1. Introduction. 1.1. Clocking in Synchronous Systems. 1.2. System Clock Design. 1.3. Timing Parameters. 1.4. Clock Signal Distribution -- Chapter 2. Theory of Clocked Storage Elements. 2.1. Latch-Based Clocked Storage Elements. 2.2. Flip-Flop -- Chapter 3. Timing and Energy Parameters. 3.1. Timing Parameters. 3.2. Energy Parameters. 3.3. Interface with Clock Network and Combinational Logic -- Chapter 4. Pipelining and Timing Analysis. 4.1. Analysis of a System that Uses a Flip-Flop. 4.2. Analysis of a System that Uses a Single Latch. 4.3. Analysis of a System with a Two-Phase Clock and Two Latches in an M-S Arrangement. 4.4. Analysis of a System with a Single-Phase Clock and Dual-Edge-Triggered Storage Elements -- Chapter 5. High-Performance System Issues. 5.1. Absorbing Clock Uncertainties. 5.2. Time Borrowing. 5.3. Time Borrowing and Clock Uncertainty -- Chapter 6. Low-Energy System Issues. 6.1. Low-Swing Circuit Techniques. 6.2. Clock Gating. 6.3. Dual-Edge Triggering. 6.4. Glitch Robust Design -- Chapter. 7 Simulation Techniques. 7.1. The Method of Logical Effort. 7.2. Environment Setup. 7.3. Appendix -- Chapter 8. State-of-the-Art Clocked Storage Elements in CMOS Technology. 8.1. Master-Slave Latch Examples. 8.2. Flip-Flop Examples. 8.3. Clocked Storage Elements with Local Clock Gating. 8.4. Low-Swing Clock Storage Elements. 8.5. Dual-Edgc-Triggered Clocked Storage Elements. 8.6. Summary -- Chapter 9. Microprocessor Examples. 9.1. Clocking for Intel Microprocessors. 9.2. Sun Microsystems Ultrasparc-III Clocking. 9.3. Alpha Clocking: A Historical Overview. 9.4. Clocked Storage Elements in IBM Processors.
Summary Provides the only up-to-date source on the most recent advances in this often complex and fascinating topic. . The only book to be entirely devoted to clocking. Clocking has become one of the most important topics in the field of digital system design. A "must have" book for advanced circuit engineers.
Note Print version record and online resource.
ISBN 9780471723707 (electronic bk.)
0471723703 (electronic bk.)
9780471723684 (electronic bk.)
0471723681 (electronic bk.)
9780471274476 (cloth)
047127447X (cloth)
ISBN/ISSN 10.1002/0471723703
OCLC # 85820227
Additional Format Print version: Digital system clocking. New York : IEEE ; Hoboken, N.J. : Wiley-Interscience, 2003 047127447X (DLC) 2002031140 (OCoLC)50315077